1. Field of the Invention
This invention is directed to methods for reducing the degree of underetching and particulate contamination occurring during dry non-isotropic etching of a polycide layer on the surface of a silicon wafer maintained in a wafer holder wherein the backside of the holder is cooled with a stream of helium gas. Specifically, in the methods of this invention, dry non-isotropic etching of the polycide layer is conducted either in the absence of backside cooling or the helium gas flow utilized in backside cooling is maintained at a pressure of no more than 3 torr.
2. State of the Art
The formation of non-isotropic patterns (i.e., essentially vertical etch profiles) on the surface of silicon wafers is essential when the thickness of the film being etched is comparable to the minimum pattern dimensions of the to-be-formed features. For example, in very large scale integration (VLSI) devices, many of the films have thickness on the order of about 0.5 to 1 microns (.mu.m) whereas the to-be-formed patterns are on the order of about 1 to 2 .mu.m. Accordingly, undercutting which accompanies typical isotropic etching methods (e.g., wet etching) becomes intolerable at these dimensions. See, for example, Wolf, "Silicon Processing for the VLSI Era", Vol. 1, Chapter 16 ("Dry Etching for VLSI Fabrication"), Lattice Press, Sunset Beach, Calif. (1986).
In view of the above, dry non-isotropic etching procedures have been developed to transfer such patterns onto silicon wafers including, by way of example, reactive ion etching, reactive ion beam etching, electron beam etching, plasma etching, and the like. Common to such dry non-isotropic etching procedures is the use of a reaction chamber wherein the silicon wafer to be etched is placed in a wafer holder. In addition to holding the wafer, the wafer holder is also used to maintain a constant wafer temperature which, among other factors, is important to ensure constant etch rates on the wafer. Typically, the wafer is maintained between 20.degree. and 60.degree. C. during dry non-isotopic etching and, if the wafer temperature is uneven over its surface, then areas of the wafer which are at higher temperatures will tend to etch faster then areas of the wafer maintained at lower temperatures. In turn, uneven etch rates can provide for undesirable uneven patterning which can reduce the degree of non-isotropic etching.
Suitable wafer holders include electrodes (which can impart a low level of heat to the wafer to maintain constant wafer surface temperatures), inert materials (which can act as a heat sink during non-isotropic etching to maintain constant wafer surface temperatures), and the like. In general, a stream of helium gas is permitted to flow to the backside of the wafer holder (the surface of the holder opposite the wafer) to further ensure constant wafer temperature which procedure is referred to as "backside cooling". Typically, in backside cooling, the flow of helium gas is set to maintain a pressure of about 10-14 tort on the backside of the wafer holder.
Notwithstanding the advantages of dry non-isotropic etching, serious problems with underetching and particulate formation are encountered when such etching is employed to remove polycides from the wafer surface. Specifically, refractory metal polycides (e.g., tungsten silicide (WSi.sub.2), molybdenum silicide (MoSi.sub.2), and the like) are employed at numerous sites of the to-be-formed circuits elements including, by way of example, metal interconnect technology, Si-gate technology, and the like, because such silicides have lower resistance, i.e., sheet resistance, as compared to polysilicon. In turn, lower sheet resistance permits the semiconductor device to be operated under faster real time conditions thereby enhancing the operating speed of the device.
In forming a layer of refractory metal polycide on the surface of such circuit elements, a layer of refractory metal or refractory metal silicide is first deposited over the entire surface of the wafer. When a refractory metal is deposited, the metal is then converted to a metal silicide by conventional methods such as thermal annealing. In either case, a layer of resist is then patterned over the surface of the wafer so as to define the to-be-formed circuit elements containing a surface of metal silicide. Next, the wafer surface is subjected to dry non-isotropic etching so as to remove the metal silicide in all areas except under the resist. Upon removal of the resist layer, a surface layer of metal silicide is found only at the desired circuit features.
It has been found, however, that the dry non-isotropic etching of the metal silicide layer on the surface of a silicon wafer utilizing backside cooling results in underetching of the wafer coupled with gross residues across the wafer surface. Both phenomena are severely deleterious to the effectiveness of the etch process as well as the wafer produced thereby. Specifically, underetching of the wafer surface and particulate contamination on the surface of the wafer can alter the functionality of the to-be-formed circuit elements.